
Appendix A
register about to Init for Date and Time. CMOS status register about to Init for Date
and Time. Refresh on and about to start 64K base memory test. Confirmed refresh
(10)DMA controller test 0 register
(10)DMA channel 1 Test. Test DMA controller 1 with AA, 55,FF,00 pattern.8237
(10)PPI disabled, Program timers 0 & 1.
(10)(Beeps)=19 short, IDT,G
(10)Initialize Power Management.(Beep)=1
1 1st 64K RAM chip or data line failure
(11)Pin23,24 of keyboard controller is blocked/unblocked. Going to check to c
pressing of <INS>key during power-
on.CMOS status register initialized.Going to
disable DMA and Interrupt controllers. Going to disable DMA and interrupt
controllers. Address line test passed. Address line test passed.
(11)DMA controller test regi
(11)DMA page register test. Test DMA page registers,use I/O ports to test address
circuits. POST enables user reboot here.Test DMA page registers. FATAL
RORS.8237 DMA,channel 1 test.
(11)Init(blast)VDU controllers.
(11)Register LDT failure.
(11)Load alternate registers with POST values.(Beep)=1
(12)Checking for pressing of <INS>key during power
on done. Going to disable
DM
A and Interrupt controllers.DMA controller#1,#2,interrupt controller#1,#2
disabled. About to disable Video display and Init port-
B. About to disable video
display and Init port-
B.64K base memory test passed. 64K base memory test
3424. Test 8254 timer 0 channel 0. Test DMA page
(12)Clear screen, turn on video.
(12)Task register failure.
(12)Restore CPU control word during warm boot. Jump t
0.(Beep)=1-2-1-
3.Test both 8237 DMA controllers. 1st 64K RAM chip or data line
(13)DMA controller#1,#2,interrupt controller#1,#2disa
Video display and initialize port-B. Chipset init
ialize/auto memory detection about
to begin. Replace first memory SIMM.(13)Chipset initialize/auto memory detection
about to begin. Check first SIMM.(13) Interrupt vectors initialized.
(13)Test 8254 timer 0 channel 1. Test
(13)LSL instruction failure.
4 1st 64K RAM chip or data line failure
bit 3. Initialize PCI Bus
ipset initialization/auto memory detection over. To un
code if compressed BIOS.8254 timer test about to start.8254 timer test about to
start.8042 keyboard controller test OK.
(14)Test 8254 timer 0 coun
ter 2. Test timer counter 2; Test 8254 timer 0 counter 2.
(14)Disable RTC interrupts.
(14)Initialize keyboard controller.(Beep)=1
st 64K RAM chip or data line failure
compressed.8254 timer about to start. CH
halfway.8254 CH-2 timer test to be complete.8254 CH-
2 timer test to be completed.
Interrupt vectors initialized. CM
(15)test 8259 interrupt mask bits for channel 1. Test 8259
channel 1 masked interrupt by alternate turning off and on the interrupt line. Test 1st
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